The AI Data Center CXL Memory Expansion and Pooling Infrastructure Market is estimated at USD 1.20 billion in 2026 and is projected to reach USD 6.83 billion by 2032, representing a CAGR of 33.6% during 2026-2032.

Market Overview

CXL extends the PCIe physical layer with cache-coherent protocols that allow processors, accelerators and memory devices to share data more efficiently than traditional peripheral I/O. CXL Type 3 devices are designed primarily for memory, while CXL switches and fabric managers allow those memory resources to be connected, pooled and allocated across multiple hosts. CXL 3.2 added stronger monitoring, management and memory-device functionality, while CXL 4.0 increases signaling to 128 GT/s and continues the roadmap toward higher-bandwidth composable infrastructure.

The immediate commercial use case is memory expansion. Controllers such as Marvell Structera X, Astera Labs Leo and Montage MXC convert CXL transactions into DDR memory accesses, allowing servers to attach more DRAM than native memory channels can support. This can reduce the need to replace a server simply because memory capacity is exhausted. Newer products also support reuse of previous-generation DDR4 alongside DDR5, creating a secondary economic benefit where operators have large existing DRAM inventories.

Memory pooling is a more significant architectural change. A CXL switch can connect multiple hosts to a shared pool of Type 3 memory devices and dynamically allocate capacity according to workload demand. Marvell's Structera S 30260 supports 16 or 32 processors or accelerators and up to 48 TB of shared memory, while LIQID offers rack-scale systems capable of provisioning CXL memory through software. Montage has demonstrated Dynamic Capacity Device operation across multiple hosts, showing how CXL memory can become an allocatable infrastructure resource rather than a fixed component of one server.

Market Drivers

• Agentic AI is increasing the memory footprint per inference workload

Long-context and multi-agent workloads retain larger amounts of model state, KV cache and working data than conventional short-context inference. Keeping all of this state in HBM is expensive and capacity constrained, while moving it repeatedly to slower storage can reduce accelerator utilization. Astera Labs is positioning fabric-attached memory as a dedicated tier for KV-cache-heavy workloads, while SK hynix has demonstrated CXL pooled-memory systems that reuse KV cache across servers and GPUs. This gives CXL a direct AI-performance role rather than limiting it to conventional server-memory expansion.

• CXL improves utilization of stranded server memory

Traditional servers bind DRAM capacity to one host even when workload demand varies over time. Memory pooling changes that model by allowing a rack-level pool to be allocated to whichever host requires it. LIQID, Marvell and Montage all emphasize dynamic allocation or sharing as a way to reduce overprovisioning and increase fleet-level utilization. The economic benefit becomes larger as DRAM capacity rises and operators face tighter memory supply, because avoiding idle capacity can reduce both hardware cost and energy consumption.

• PCIe 6 and CXL 3.2 increase bandwidth available to external memory

Earlier CXL deployments were often capacity-oriented because the external memory path was slower than local DRAM. The transition to PCIe 6 and CXL 3.2 increases link speed to 64 GT/s and supports higher-bandwidth controller and switch architectures. Astera Labs, Montage and Marvell all introduced or sampled CXL 3.x products during 2026. Higher link performance expands the range of workloads that can use CXL-attached memory without excessive latency or bandwidth penalties.

• Rack-scale products are moving CXL beyond individual add-in cards

Commercial systems are increasingly integrating many memory modules, CXL switches and fabric-management software into shared rack-scale platforms. LIQID markets SmartStack pooled-memory systems, Primemas is developing JBOM systems reaching tens to more than 100 TB, and the CXL Consortium highlighted rack-scale pooled-memory demonstrations at AI Infra Summit and Future of Memory and Storage 2026. This changes the addressable market from semiconductor controllers alone to complete memory-infrastructure systems and associated management software.

Restraints and Adoption Challenges

CXL adoption remains constrained by software maturity, platform interoperability and workload sensitivity to latency. Not every AI workload benefits from a larger but slower memory tier, and software must understand where data should reside across HBM, local DRAM, CXL memory and storage. Multi-host pooling also requires fabric management, operating-system support and disciplined fault isolation. Hyperscalers can develop custom memory architectures, limiting merchant opportunity in selected fleets. Finally, the economics depend on memory pricing: if local DRAM becomes inexpensive and abundant, some expansion and pooling projects deliver less compelling savings.

Segment Analysis

By Component

CXL memory-expansion controllers represent the largest dedicated 2026 revenue pool because they are required inside Type 3 memory cards, EDSFF modules and expansion appliances. These controllers manage protocol translation, memory channels, reliability functions, telemetry and security. Marvell Structera X, Astera Labs Leo and Montage MXC illustrate the increasingly competitive controller market across CXL 2.0 and CXL 3.2 generations.

CXL switches are expected to grow fastest through 2032 as deployments move from one-host expansion toward shared memory and rack-scale disaggregation. Switches create the fan-out, routing and dynamic allocation required for multi-host memory pools. Near-memory accelerators and full pooled-memory appliances also expand rapidly from a smaller base because they add processing, compression or software-defined resource management around the memory tier rather than simply exposing additional capacity.

Market and Technology Indicators

Regional Opportunity

North America

North America is the leading market for AI data-center CXL memory infrastructure because the United States concentrates hyperscale cloud providers, AI labs, CXL silicon vendors and memory-system startups. Marvell and Astera Labs are developing CXL controllers and switches for hyperscale deployments, LIQID commercializes pooled-memory systems, and Micron participates in large CXL memory projects including the Primemas Abaco architecture for Pacific Northwest National Laboratory. Intel, AMD and NVIDIA provide the processor and accelerator platforms that determine CXL attachment and software support.

The strongest near-term opportunity is capacity expansion and memory reuse. Hyperscale cloud fleets contain large volumes of servers where CPU performance remains adequate but memory capacity or bandwidth constrains deployment. CXL allows operators to add memory without replacing the complete host, and new controller families support both DDR4 and DDR5 to improve utilization of installed memory inventory. This creates a commercial path before full rack-scale disaggregation becomes standard.

AI inference expands the use case. Long-context and agentic workloads require larger memory tiers for KV cache, graph data, vector databases and persistent agent state. Astera Labs, Marvell, SK hynix and LIQID are all positioning CXL memory against these workloads rather than only general-purpose cloud computing. Through 2032, North American growth is expected to shift progressively from individual expansion cards toward switched memory pools and fabric-attached accelerator memory.

Asia Pacific is a major supply region because Samsung Electronics, SK hynix and other memory manufacturers are developing CXL memory modules and collaborating with controller vendors such as Montage Technology and Primemas. Europe participates through hyperscale deployments, HPC and semiconductor IP. The Middle East remains an emerging demand region where new AI campuses can adopt memory-disaggregated architectures without the compatibility constraints of older server fleets.

Competitive Landscape

The competitive landscape spans CXL controller and switch suppliers, memory manufacturers, system vendors and software-defined composable-infrastructure companies. Marvell has built a broad CXL portfolio across expansion controllers, near-memory accelerators and switches and strengthened that position through the 2026 acquisition of XConn. Astera Labs competes strongly in hyperscale memory controllers and is extending Leo into direct fabric-attached AI memory. Montage Technology is advancing CXL 3.2 controllers, retimers and dynamic-capacity implementations.

Memory manufacturers influence adoption because CXL devices ultimately depend on qualified DRAM and module designs. SK hynix is demonstrating pooled and compute-enabled CXL memory for AI, while Samsung Electronics and Micron participate in module development, validation and large memory-system programs. Primemas is building high-capacity CXL memory systems with Micron and Samsung collaboration, while LIQID combines CXL hardware with software-defined orchestration to deliver rack-scale pooling.

Competitive differentiation centers on CXL generation, bandwidth, memory-channel count, reliability and serviceability, security, platform interoperability, pooling features, fabric-management software and the ability to demonstrate measurable AI workload gains. The market is likely to favor vendors that can prove compatibility across CPUs, GPUs, memory suppliers and operating systems rather than isolated component performance.

Major companies and ecosystem participants covered: Marvell Technology, Astera Labs, Montage Technology, SK hynix, Samsung Electronics, Micron Technology, LIQID, Primemas, Intel, AMD, NVIDIA, Microchip Technology, Cadence Design Systems, Synopsys and UnifabriX.

Recent Developments

• September 2026: Astera Labs expanded its Leo Smart Memory Controller family with CXL 3.2 memory expansion and pooling products for agentic AI and hyperscale cloud workloads.

• September 2026: Marvell demonstrated an end-to-end CXL memory architecture with Intel combining Structera X expansion, Structera S switching and PCIe/CXL retiming.

• September 2026: Marvell demonstrated Structera X interoperability with NVIDIA Vera, extending CXL expansion into next-generation AI CPU platforms.

• August 2026: SK hynix demonstrated pooled-memory AI-agent serving and long-context inference using CXL memory at Future of Memory and Storage 2026.

• August 2026: Primemas showcased a CXL full-stack portfolio and a 100 TB-class shared-memory architecture being developed with Micron for Pacific Northwest National Laboratory.

• July 2026: Montage Technology announced trial production of a CXL 3.2 Memory eXpander Controller supporting PCIe 6.x, DDR5 and memory pooling.

• March 2026: Marvell launched the 260-lane Structera S 30260 CXL switch for rack-level memory pooling, with customer sampling planned for the third quarter of 2026.

• February 2026: Marvell completed its acquisition of XConn Technologies, adding production CXL switching silicon to its AI connectivity portfolio.

AI Data Center CXL Memory Expansion and Pooling Infrastructure Market Scope: